The present invention generally relates to transistor gate dielectrics and methods of fabricating the same. More particularly, the invention relates to processes and structures for improving tunnel oxide quality in erasable programmable read-only memories (EEPROMs).
Memory devices such as erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), or flash erasable programable read-only memories (FEPROMs) are erasable and reusable memory cells which are used in digital cellular phones, digital cameras, LAN switches, cards for notebook computers, etc. A memory cell operates by storing electric charge (representing an xe2x80x9conxe2x80x9d state) on an electrically isolated floating gate, which is incorporated into a transistor. This stored charge affects the behavior of the transistor, thereby providing a way to read the memory element. It is therefore crucial that the memory cell be able to maintain the stored charge over time, so that charge leakage does not cause data errors by converting xe2x80x9conxe2x80x9d states to xe2x80x9coff.xe2x80x9d
A memory cell typically consists of a transistor, a floating gate, and a control gate above the floating gate in a stacked gate structure. The floating gate, typically composed of polysilicon, is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer, which is typically formed of silicon oxide. Because charge is transferred across the dielectric layer by quantum-mechanical tunneling, this dielectric layer is often referred to as a xe2x80x9ctunnel oxidexe2x80x9d layer. Such tunnel oxide layers are typically approximately 100 xc3x85 thick. Properties of the tunnel oxide must be strictly controlled to ensure the ability to read and write by tunneling, while avoiding data loss through charge leakage. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer, such as oxide-nitride-oxide (ONO). Electrical access to the floating gate is therefore only through capacitors.
Storing charge on the floating gate programs a memory cell. This is achieved via hot-electron injection by applying a high positive voltage (approximately 12 V) to the control gate, and a high drain-to-source bias voltage (approximately 6 V). An inversion region is created between the source and drain by the control gate voltage, and electrons are accelerated from the source to the drain by the drain bias voltage. Some fraction of these electrons will have sufficient energy to surmount the tunnel oxide barrier height and reach the floating gate. The floating gate is therefore programmed by collecting and storing these electrons to represent an xe2x80x9conxe2x80x9d state.
An EPROM device can be erased (i.e., returned to an xe2x80x9coffxe2x80x9d state) by exposing the floating gate to ultraviolet light, which excites the stored electrons out of the floating gate. The erasure of an EEPROM or FEPROM cell is accomplished via Fowler-Nordheim tunneling, in which an electric field is sufficient for the stored electrons to traverse the tunnel oxide and enter the substrate, thereby reducing the stored charge in the floating gate. Under this mechanism for discharging the floating gate, a large negative voltage (e.g., xe2x88x9210 V) is applied to the control gate, and a positive voltage (e.g., 5-6 V) is applied to the source while the drain is left floating. Electrons then tunnel from the floating gate through the tunnel oxide, and are accelerated into the source. Because both the programming and erasing of a memory element takes place via charge transfer processes across the tunnel oxide layer, it is important to minimize the density of interface states and other defects in the form of charge traps in this region which would otherwise create a mechanism for charge leakage through the tunnel oxide.
Current memory devices have shown improvements in data retention by the formation of a thin oxynitride layer, typically formed by exposure of the thermal oxide to either NO or N2O at elevated temperatures. The thin nitrided interface improves the tunnel oxide""s resistance to the creation of defects by electrons during the write and erase sequence. Another possible method of reducing charge leakage is to remove species such as hydroxyl (OH) from the tunnel oxide prior to final encapsulation. Nitridation also forms a barrier against further degradation by impurity migration. The density of charge trapping sites due to OH in the tunnel oxide region is thereby significantly reduced, resulting in devices With improved data retention and reliability.
Once the stacked gate structure has been fabricated and etched the appropriate dimensions, the stacked gate structure is encapsulated in a liner layer, followed by the formation of an insulating layer, typically composed of thick, planarized borophosphosilicate glass (BPSG). The liner layer between the source/drain regions and the BPSG, often composed of a low pressure chemical vapor deposition (LPCVD) oxide, serves to minimize out-diffusion of contaminants and dopants from the BPSG. Such out-diffusion might otherwise affect the performance of underlying devices.
Additional improvements in memory device performance have been achieved by performing xe2x80x9calloyxe2x80x9d steps later in the fabrication process. In an alloy step, the integrated circuit being fabricated is exposed to hydrogen while being annealed at low temperatures (less than 450xc2x0 C.). Incorporation of hydrogen is believed to tie up dangling bonds at the tunnel oxide region, thereby eliminating interface states that would otherwise contribute to charge trapping and device degradation. The positive effects of alloy steps are well known in the art. Unfortunately, hydrogen annealing and/or OH exposure at high temperatures can be deterimental to transistor devices. See, e.g., Vanheusden et al., xe2x80x9cPositive Charging of Buried SiO2 by Hydrogenation,xe2x80x9d Appl. Phys. Lett., Vol. 64, No. 19 (May 9, 1994), pp. 2575-77. Typical oxide liners are not effective barriers against H2 or OH. Accordingly, high temperature processing allows mobile OH molecules to diffuse into the tunnel oxide after formation, degrading data retention of the resultant part.
While processes have been developed to improve gate dielectric quality, as measured by improved data retention in flash memory devices, for example, a finite soft error rate remains. Accordingly a need exists for further improvements in the fabrication of transistor gate dielectrics.
In accordance with one aspect of the present invention, a method is provides for fabricating an integrated circuit. The method includes forming a dielectric layer on a semiconductor surface and exposing the dielectric layer to a hydrogen-bearing nitrogen source. A conductive layer is then deposited directly over the dielectric layer. After patterning to define a gate stack, a conformal insulating liner is formed over the gate stack. The liner incorporates nitrogen.
In accordance with another aspect of the invention, an integrated circuit is provided with a plurality of transistors. Each transistor includes a hydrogen-passivated gate dielectric layer, a stacked gate structure above the gate dielectric layer, and a conformal liner layer covering the stacked gate structure. The liner layer includes nitrogen.
In the illustrated embodiments, a tunnel oxide in an EEPROM device is nitrided with ammonia. Hydrogen is thus incorporated into the tunnel oxide, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a silicon nitride or oxynitride.
Advantageously, the liner serves as an excellent diffusion barrier against contamination of the gate stack from hydrogen or OH, particularly protecting the tunnel oxide. While such effective diffusion barriers also inhibit hydrogen diffusion from subsequent alloy steps, meant for occupying dangling bonds at the substrate and tunnel oxide interface, the prior ammonia nitridation compensates for this hydrogen blocking by providing hydrogen to the oxide prior to sealing the gate stack with the liner.